The present invention relates to a semiconductor integrated circuit device and technology for manufacturing the semiconductor integrated circuit device, and in particular relates to the technology effectively applied to the manufacture of a semiconductor integrated circuit device including fine semiconductor elements and wirings.
Conventionally, in the layout design of a semiconductor integrated circuit device, power-feeding diffusion layers are extended in one direction and MOS transistors constituting a desired circuit are arranged therebetween, and these are recognized as a cell. One example of such a cell layout is described in Japanese patent laid-open No. 2006-253375, for example. Moreover, a power-feeding diffusion layer formed so as to extend in one direction may be referred to as a “tap”.
Japanese patent Laid-Open No. 11-135734 discloses a technology, wherein in a semiconductor device having a diode comprising a drain region and a p-type well, suppose that a distance between one edge of a contact in the drain region and an edge of a contact in the well tap region is L1 and a distance between other edge of the contact in the drain region and an edge of other contact in the well tap region is L2, then L2≧L1. By setting such a condition, electrostatic destruction (ESD) without avalanche breakdown in the diode is effectively prevented.
Japanese patent laid-open No. 2007-73885 discloses a technology that enables multiple types of power supplies without damaging the degree of integration in a semiconductor integrated circuit device comprising a plurality of basic cells.
Japanese patent laid-open No. 2006-228982 discloses a technology, wherein in a semiconductor integrated circuit device in which a plurality of standard cells having a circuit diffusion layer for forming a circuit is arranged, if the circuit diffusion layers of the adjacent standard cells are arranged at predetermined intervals and formed with mutually different phases, then a tap diffusion layer for forming a power supply potential or an earth potential in the vicinity of the relevant adjacent circuit diffusion layers is formed discontinuously. Thereby, a high degree of integration of patterns is relatively easily achieved without reducing the pattern resolution and without causing problems such as phase discrepancy.